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RTAX-DSP Radiation-Tolerant FPGAs
Radiation Performance
* SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy (TMR) - Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg - SEU Rate < 10-10 Errors/Bit-Day in Worst-Case Geosynchronous Orbit Expected SRAM Upset Rate of <10-10 Errors/Bit-Day with Use of Error Detection and Correction (EDAC) IP (included) with Integrated SRAM Scrubber - Single-Bit Correction, Double-Bit Detection - Variable-Rate Background Refreshing Total Ionizing Dose Up to 300 krad (Si, Functional) Single-Event Latch-Up Immunity (SEL) to LETTH > 117 MeV-cm2/mg TM1019 Test Data Available
Leading-Edge Performance
* * * * High-Performance Embedded FIFOs 350+ MHz System Performance 500+ MHz Internal Performance 700 Mbps LVDS Capable I/Os
*
Specifications
* * * * * Up to 4 Million Equivalent System Gates or 500 k Equivalent ASIC Gates Up to 16,800 SEU-Hardened Flip-Flops Up to 840 I/Os Up to 540 kbits Embedded SRAM Manufactured on Advanced 0.15 m CMOS Antifuse Process Technology, 7 Layers of Metal
* * *
Features
* * * Single-Chip, Nonvolatile Solution 1.5 V Core Voltage for Low Power Flexible, Multi-Standard I/Os: - 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation - Bank-Selectable I/Os - 8 Banks per Chip - Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3 V PCI - JTAG Boundary Scan Testing (as per IEEE 1149.1) - Differential I/O Standards: LVPECL and LVDS - Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 - Hot-Swap Compliant with Cold-Sparing Support (Except PCI) Embedded Memory with Variable Aspect Ratio and Organizations: - Independent, Width-Configurable Read and Write Ports - Programmable Embedded FIFO Control Logic - ROM Emulation Capability Deterministic, User-Controllable Timing Unique In-System Diagnostic and Debug Capability
Embedded Multiply/Accumulate Blocks
* * * * Up to 120 Multiply/Accumulate Blocks Fully SEU- and SET-Hardened 125 MHz Performance throughout Military Temperature Range Flexible, Cascadable Accumulate Function
Processing Flows
* * * B-Flow - MIL-STD-883B E-Flow - Actel Extended Flow EV-Flow - Class V Equivalent Flow Processing *
Prototyping Options
* RTAX-DSP PROTO Devices with Same Functional and Timing Characteristics as Flight Unit in a Non-Hermetic Package * *
Table 1 *
RTAX-DSP Family Product Profile RTAX2000D 2,000,000 250,000 8,960 17,920 17,920 64 64 288 k 4 4 8 684 2,052 1152 RTAX4000D 4,000,000 500,000 16,800 33,600 33,600 120 120 540 k 4 4 8 840 2,520 1272
Device Capacity Equivalent System Gates ASIC Gates Modules Register (R-cells) Combinatorial (C-cells) Flip-Flops (maximum) Embedded Multiply / Accumulate Blocks DSP Mathblocks Embedded RAM/FIFO (without EDAC) Core RAM Blocks Core RAM Bits (k = 1,024) Clocks (segmentable) Hardwired Routed I/Os I/O Banks User I/Os (maximum) I/O Registers Package CCGA/LGA
S ep t e m b e r 2 0 0 8 (c) 2008 Actel Corporation
i See the Actel website for the latest version of the datasheet.
RTAX-DSP Radiation-Tolerant FPGAs
Ordering Information
RTAX2000D _ CG 1152 B Application B = MIL-STD-883 Class B E = E-Flow (Actel Space-Level Flow) EV = Class V Equivalent Flow Processing Package Lead Count Package Type CG = Ceramic Column Grid Array LG = Land Grid Array Speed Grade Blank = Standard Speed Part Number RTAX2000D = 2,000,000 Equivalent System Gates RTAX4000D = 4,000,000 Equivalent System Gates
Temperature Grade Offerings
Package CG1152/LG1152 CG1272/LG1272 RTAX2000D B, E, EV - RTAX4000D - B, E, EV
Note: *The CCGA offerings (1152 and 1272) are offered with Six Sigma columns. B = MIL-STD-883 Class B E = E-Flow (Actel Space-Level Flow) EV = Actel "V" Equivalent Flow
Speed Grade and Temperature Grade Matrix
Std. B E EV
Contact your local Actel representative for device availability.
Device Resources
Device CG484/LG1152 CG896/LG1272 User I/Os (including clock buffers) RTAX2000D RTAX4000D 684 - - 840
Note: CCGA = Ceramic Column Grid Array, LGA = Land Grid Array
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RTAX-DSP Radiation-Tolerant FPGAs
Actel MIL-STD-883 Class B Product Flow
Table 2 * Step 1 2 3 4 5 6 7 8 9 10 11 Internal Visual Serialization Temperature Cycling Constant Acceleration Particle Impact Noise Detection Seal (Fine & Gross Leak Test) Pre-Burn-In Electrical Parameters Dynamic Burn-In Interim (Post-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test a. Static Tests (1) 25C (2) -55C and +125C b. Functional Tests (1) 25C (2) -55C and +125C c. Switching Tests at 25C 12 External Visual 1010, Condition C, 10 cycles minimum 2001, Y1 Orientation Only Condition TBD 2020, Condition A 1014 In accordance specification with applicable Actel device Actel MIL-STD-883 Class B Product Flow for RTAX-DSP* Screen 2010, Condition B Method Requirement 100% 100% 100% 100% 100% 100% 100% 100% 100% All Lots device 100%
1015, Condition D, 160 hours at 125C or 80 hours at 150C minimum In accordance specification 5% In accordance with applicable Actel specification, which includes a, b, and c: 5005, Table 1, Subgroup 1 5005, Table 1, Subgroup 2, 3 with applicable Actel device
5005, Table 1, Subgroup 7 5005, Table 1, Subgroup 8a, 8b 5005, Table 1, Subgroup 9 2009 100%
Note: *For CCGA devices, all Assembly, Screening, and TCI testing is performed at LGA level. Only QA electrical and mechanical visual tests are performed after solder column attachment.
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RTAX-DSP Radiation-Tolerant FPGAs
Actel Extended Flow
Table 3 * Step 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Destructive Bond Pull Internal Visual Serialization Temperature Cycling Constant Acceleration Particle Impact Noise Detection Radiographic (X-Ray) Pre-Burn-In Electrical Parameters Dynamic Burn-In 1010, Condition C, 10 cycles minimum 2001, Y1 Orientation Only Condition TBD 2020, Condition A 2012, One View (Y1 Orientation) Only In accordance with applicable Actel device specification 1015, Condition D, 240 hours at 125C or 120 hours at 150C minimum 1015, Condition C, 72 hours at 150C or 144 hours at 125C minimum In accordance with applicable Actel device specification 5% Overall, 3% Functional Parameters at 25C In accordance with applicable Actel specification, which includes a, b, and c: 5005, Table 1, Subgroup 1 5005, Table 1, Subgroup 2, 3 device 100% 100% 100% 100% All Lots 100% 100% 100% Actel Extended Flow for RTAX-DSP1, 2, 3 Screen
4
Method 2011, Condition D 2010, Condition A
Requirement Extended Sample 100% 100% 100%
Interim (Post-Dynamic-Burn-In) Electrical Parameters In accordance with applicable Actel device specification Static Burn-In Interim (Post-Static-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test
4
a. Static Tests (1) 25C (2) -55C and +125C b. Functional Tests (1) 25C (2) -55C and +125C c. Switching Tests at 25C 15 16 Notes: Seal (Fine & Gross Leak Test) External Visual
5005, Table 1, Subgroup 7 5005, Table 1, Subgroup 8a, 8b 5005, Table 1, Subgroup 9 1014 2009 100% 100%
1. Actel offers Extended Flow for users requiring additional screening beyond MIL-STD-833, Class B requirement. Extended Flow incorporates the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. 2. The Quality Conformance Inspection (QCI) for Extended Flow devices still complies to the MIL-STD-833, Class B requirement. 3. For CCGA devices, all Assembly/Screening/TCI testing is performed at LGA level. Only QA electrical and mechanical visual tests are performed after solder column attachment. 4. Requirement for 100% nondestructive bond pull per Method 2003 is substituted by an extensive destructive bond pull to Method 2011 Condition D on an extended sample basis.
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RTAX-DSP Radiation-Tolerant FPGAs
Actel "EV" Flow (Class V Flow Equivalent Processing)
Table 4 * Step 1 2 3 4 5 6 7 8 9 Destructive Bond Pull Internal Visual Serialization Temperature Cycling Constant Acceleration Particle Impact Noise Detection Radiographic (X-Ray) Pre-Burn-In Electrical Parameters Dynamic Burn-In 1010, Condition C, 50 cycles minimum 2001, Y1 Orientation Only Condition TBD 2020, Condition A 2012, One View (Y1 Orientation) Only In accordance specification with applicable Actel device Actel "EV" Flow (Class V Equivalent Flow Processing) for RTAX-DSP1, 2 Screen
3
Method 2011, Condition D 2010, Condition A
Requirement Extended Sample 100% 100% 100% 100% 100% 100% 100% 100%
1015, Condition D, 240 hours at 125C or 120 hours at 150C minimum with applicable Actel device
10 11 12 13 14
Interim (Post-Dynamic-Burn-In) Electrical Parameters In accordance specification Static Burn-In Interim (Post-Static-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test
3, 4
100% 100% 100% All Lots 100%
1015, Condition C, 72 hours at 150C or 144 hours at 125C minimum In accordance specification with applicable Actel device
5% Overall, 3% Functional Parameters at 25C In accordance with applicable Actel specification, which includes a, b, and c: 5005, Table 1, Subgroup 1 5005, Table 1, Subgroup 2, 3 device
a. Static Tests (1) 25C (2) -55C and +125C b. Functional Tests (1) 25C (2) -55C and +125C c. Switching Tests at 25C 15 16 17 Notes: Seal (Fine & Gross Leak Test) External Visual Wafer Lot Specific Life Test (Group C)
5005, Table 1, Subgroup 7 5005, Table 1, Subgroup 8a, 8b 5005, Table 1, Subgroup 9 1014 2009 MIL-PRF-38535, Appendix B, sec. B.4.2.c 100% 100% All Wafer Lots
1. Actel offers "EV" flow for users requiring full compliance to the MIL-PRF-38535 Class V requirement. The "EV" process flow is expanded from the existing E-flow requirement (it still meets the full SMD requirement for current E-flow devices) with the intention to be in full compliance to the MIL-PRF-38535 Table IA and Appendix B requirement, but without the official Class V certification from DSCC. 2. For CCGA devices, all Assembly/Screening/TCI testing is performed at LGA level. Only QA electrical and mechanical visual tests are performed after solder column attachment. 3. The requirement for 100% nondestructive bond pull per Method 2003 is fulfilled by substitution of an extensive extended sample basis. 4. Read and record performed at -55C and +125C (no delta calculation).
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RTAX-DSP Radiation-Tolerant FPGAs
General Description
RTAX-DSP Mathblock Functional Description
The flexible elements of the RTAX-DSP Mathblocks enable easy integration into many different signal processing topologies, such as Fast Fourier Transforms, Inverse Fast Fourier Transforms, Finite Impulse Response Filters, Infinite Impulse Response Filters, and Discrete Cosine Transforms. The hardwired Mathblocks also enable acceleration of high precision single- and doublefloating point multiplications. Figure 1-1 shows a basic functional diagram of a Mathblock. The multiplier can be fractured to implement two instances of signed 9x9 multiplication (Figure 1-3).
A1[8:0]
X
B1[8:0]
P1[17:0]
A2[8:0] ADD_SUB A[17:0] OVFL
X
B2[8:0]
P2[17:0]
X
B[17:0] SHIFT17 SEL_CONST CONST[40:0] SEL_CASC
+/>>17
D EN
SN[40:0]
Figure 1-3 * Mathblock Configured with Two Independent Signed 9x9 multipliers
2. Adder/Subtractor plus MUX Control
MUX2
*
The adder/subtractor can perform the following functions: - - - Accumulate using feedback. Create higher precision multipliers using the SN-1 input and the 17-bit shift function. Create complex DSP functions, such as FIR filters, by cascading Mathblocks together using the SN-1 input. The initial value of the accumulate function can be set using the value defined on the CONST bus.
MUX1
SN-1[40:0]
Figure 1-1 * RTAX-DSP Mathblock
The Mathblocks comprise the following elements: 1. Multiplier The multiplier operates on two signed 18-bit factors, A[17:0] and B[17:0] (Figure 1-2). The multiplier produces a signed 36-bit output, which is provided as an input to the add/subtract function. The output of the multiplier can optionally bypass the add/subtract function. -
Overflow or underflow of the add/subtract function is indicated by the OVFL output. Figure 1-4 shows the Mathblock configured to perform multiply and accumulate functions. FPGA resources can be used to extend the accumulate width.
A[17:0]
ADD_SUB A[17:0] OVFL
X
B[17:0]
P[35:0] B[17:0]
X
SEL_CONST CONST[40:0]
+/-
SN[40:0]
Figure 1-2 * RTAX-DSP Mathblock Multiplier Configured as Signed 18x18
Figure 1-4 * Mathblock Configured to Perform Multiply and Accumulate Functions
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RTAX-DSP Radiation-Tolerant FPGAs
3. Output Register The output of the adder/subtractor block is presented to a 41-bit output register. The register has a clock input, an enable input, a set or reset input, and provides a 41-bit output SN[40:0] to the exterior of the Mathblock. Signals SN[40:0] are also fed back within the Mathblock to the accumulator multiplexer stack to enable various accumulation functions. 4. Cascading Mathblocks Mathblocks may be cascaded together to form complex DSP structures such as FIR filters and FFTs. Figure 1-5 shows the configuration of Mathblocks cascaded together.
A[17:0]
Next Mathblock
X
B[17:0] CASC_CTL A[17:0]
+/Cascade MUX
P2[40:0]
X
B[17:0]
+/Cascade MUX
P1[40:0]
Previous Mathblock
Figure 1-5 * Mathblocks Cascaded Together as Part of a Complex DSP Function
RTAX-DSP Architecture
The overall RTAX-DSP device architecture is shown in Figure 1-6. In each core tile, there are four Mathblocks, which are located adjacent to the SRAM/FIFO blocks. The Mathblocks are evenly distributed across the device, to help achieve uniform performance of DSP functions.
SuperCluster
C C R
TX RX TX RX B TX RX TX RX
C
C
R
Core Tile
DSP Mathblock 4 k RAM/FIFO
RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC DSP I/F DSP I/F DSP I/F DSP I/F DSP I/F DSP I/F DSP I/F DSP I/F DSP I/F DSP I/F DSP I/F DSP I/F DSP I/F SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC RAMC RAMC RAMC RAMC RAMC DS SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC
4 k RAM/FIFO
4 k RAM/FIFO
4 k RAM/FIFO
Chip Layout
SC SC ADD_SUB
A[17:0]
OVFL
I/O Structure
B[17:0]
X
SHIFT17
+/-
>> 17
D EN
SN[40:0]
SEL_CONST CONST[40:0] SEL_CASC
MUX2
MUX1
SN-1[40:0]
Mathblock
Figure 1-6 * RTAX-DSP Device Architecture Overview
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w w w. a c t e l . c o m
Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. River Court,Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540 Actel Japan EXOS Ebisu Buillding 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 http://jp.actel.com Actel Hong Kong Room 2107, China Resources Building 26 Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 www.actel.com.cn
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